In integrated circuits, electrostatic discharge (ESD) stress events may arise when a charged object, such as a human body or another machine, is placed in proximity to an integrated circuit device and a static discharge occurs. The conductive leads on a packaged integrated circuit (IC) constitute an efficient surface for receiving electrostatic discharge. If the voltage stress that is caused by the discharge into an IC pin is not protected against, physical damage including breakdown, metal electromigration, gate oxide rupture and other damage due to an ESD stress may destroy or damage the physical devices within the integrated circuit.
Prior art ESD protection approaches involve a variety of circuit elements that are associated with the pads of the integrated circuit. Typically, a bond wire couples the input/output pad, which is a metallic or conductive surface, to a package pin. The pins may be gold, copper, palladium and nickel plated material or the like. The ESD protection circuit provides a path to a safe terminal, typically a power supply pin or ground pin, and causes the electro-static current (called a “strike”) to bypass the susceptible semiconductor devices formed within the integrated circuit. An effective ESD circuit can protect a device and prolong its life.
The level of ESD protection needed for integrated circuits varies widely depending on the application and the type of integrated circuits. Circuits intended for use in automobile applications require particularly robust ESD protection. Similarly, integrated circuits that are intended to be handled by a consumer, such as flash cards and DIMM modules that a consumer physically inserts into a board or slot are particularly vulnerable to human body ESD strikes. In contrast, circuits that are installed into a robust circuit board inside a factory setting and placed on a well protected system in a highly controlled environment may require far less robust ESD protection. The work stations, workers, and the tools used in such an environment can be strapped to a ground terminal, and the humidity and materials used in the environment can be controlled to lower the probability of a static discharge event. In some cases, this protection may lower the ESD probability to a level such that on-board protection circuitry may not be required. This is a rare case, however, and most integrated circuits have some on-board ESD circuitry.
The electronics industry has created standards and classes for ESD ratings of devices, so that the purchasers of an integrated circuit may know what level of protection or class of ESD event the integrated circuit is designed for. These may be described as classes of protection for a human body model (HBM) event, for example. Class 0 may be for events from 0-2 kilovolts, Class 1 may be from 2 kilovolts to 4 kilovolts, Class 2 may be for greater than 4 kilovolts. Machine model (MM) events are also specified. This information is typically provided by an IC manufacturer so that the buyer understands what ESD stresses the device typically can withstand. Another test framework known as the charged device model (CDM) has been gaining popularity recently for ESD testing because it provides a more practical real world ESD test. The CDM simulates what happens when an IC, in an automated manufacturing environment, becomes electrically charged (e.g., by coming into contact with another material and then being separated from that other material) and then discharges due to contact or proximity with a conductor referenced to another potential or to ground.
ESD events typically happen between an input, input/output or output pad and another terminal, either VSS (ground) and VDD (positive power supply). Four modes of ESD stress are commonly described. A positive voltage from a pad to VSS may be referred to as a PS strike, a positive voltage from a pad to VDD may be referred to as a PD strike, a negative voltage from a pad to VSS may be referred to as an NS strike, and a negative voltage from a pad to VDD may be referred to as a ND strike. These terms for ESD stress modes are used herein.
ESD circuits have used silicon controlled rectifier (SCR) structures previously to provide a current path. SCR devices are known in the art to be formed from p-n-p-n or n-p-n-p junctions. Once an SCR device is triggered, it will continue to conduct current so long as an adequate hold current is present, and the low on-resistance Ron for SCR devices and low triggering voltage renders SCR devices particularly useful in ESD protection circuits.
A challenge associated with the use of SCR structures as ESD clamps has been the relatively low turn-on speed (i.e., relatively long turn-on time) provided by such an approach, which has resulted in low CDM performance. The CDM discharge is a fast transient pulse, which may occur over several nanoseconds as an upper limit. Turn-on efficiency is therefore a factor that impacts ESD performance, e.g., for CDM testing.